In the microelectronic fabrication industry, there is often a need to evaluate the effect of local process variability on individual transistors across a chip. For example, often times data pertaining to electrical properties of field effect transistors (FETs) based on variations in a process is required. More specifically, it may be required to evaluate the variation of PFET and NFET threshold voltage with respect to process environment variations experienced during fabrication. As an example, threshold voltage (Vt) may vary within a chip; for example, due to variations in gate length caused by reactive ion etching (RIE) load variation or photo resist planarization variations. In another example, a pattern density of various material stacks can modulate the rapid thermal anneal (RTA) temperature locally and may cause as much as 100 mV variation in threshold voltage (Vt) within a chip. One approach to this problem is to measure an electrical property of multiple transistors and then to characterize across chip variation based on those measurements. This approach, however, can require a very large sample size of transistors to provide adequate data for variations over many length scales. For example, the characterization does not enable an evaluation of a direction of the process environment variation on the chip.
Within chip variation impact on product power-performance and circuit functionality is increasingly important. Various structures have been developed to monitor the within chip variation, and currently the most powerful solution is to place embedded within-chip variation monitor or intra die variation monitors (IDVMON). IDVMON is a small structure containing a few key devices that can be subsequently measured; IDVMON are placed numerous times across chip, in space not used by other circuits or structures. The threshold voltage and device current may be measured for a transistor that is part of IDVMON. When a resistor is utilized the resistance variation amongst the multiple IDVMONs utilized. In addition to quantification of within-chip variation, IDVMON can also serves as a structure to debug and calibrate product line-centering by measuring the product-kerf offset. Direct measurement of across-chip variation provides detailed information for variation reduction efforts. Identical structures to monitor offset between functional blocks and provide guidelines for line centering.
Measuring the electrical properties of devices embedded in IDVMON currently requires additional CA and M1 masks (contact A and metal 1 masks), which may result in a cost increases. The IDVMON specific CA/M1 masks are used to wire IDVMON to large probe pads, which will enable test. The probe pads consume large area, particularly on M1. Therefore within chip variation monitors and product and characterization circuits cannot be wired up on the same wafer as a standard production wafer because the IDVMON CA/M1 layers will consume large amount of metal wiring space. Therefore the IDVMON CA/M1 is different from the POR mask. POR is a process of record mask or standard mask which utilizes standard procedures for manufacture. Wafers running with an IDVMON mask, have to be sacrificed which prevents characterizing these structures frequently in production runs.
Recently, there is a strong demand to enable a 3D VLSI chip by stacking two or more chips. 3D VLSI chips employ Through-Silicon Vias (TSVs) in the wafer. The devices used in 3D VLSI chips may have different device characteristics from those in conventional 2D VLSI chips because of the proximity effect between device and TSV, and wafer thinning effect. It is important to study the 3D process impact on device variability during development and manufacturing. The purpose of this invention is to provide an IDVMON for 3D VLSI chips development and manufacturing.